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may 2015 docid025074 rev 3 1 / 14 this is information on a product in full produ ction. www.st.com STL23NS3LLH7 n - channel 30 v, 0.0027 ? typ., 23 a stripfet? h7 power mosfet plus monolithic schottky in a powerflat? 3.3 x 3.3 datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max i d STL23NS3LLH7 30 v 0.0037 ? 23 a ? very low on - resistance ? very low q g ? high avalanche ruggedness ? embedded schottky diode applications ? switching applications description this n - channel power mosfet utilizes the stripfet h7 technology with a trench gate structure combined with extremely low on - re sistance. the device also offers ultra - low capacitances for higher switching frequency operations. table 1: device summary order code marking package packing STL23NS3LLH7 23ns3 powerflat tm 3.3 x 3.3 tape and reel d(5, 6, 7, 8) g(4) s(1, 2, 3)
contents STL23NS3LLH7 2 / 14 docid025074 rev 3 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 2.1 electrical characteristics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 8 4 package information ................................ ................................ ....... 9 4.1 powerflat 3.3 x 3.3 package information ................................ ........ 10 5 revisio n history ................................ ................................ ............ 13
STL23NS3LLH7 electrical ratings docid025074 rev 3 3 / 14 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v ds drain - source voltage 30 v v gs gate - source voltage 20 v i d (1) drain current (continuous) at t pcb = 25 c 23 a i d (1) drain current (continuous) at t pcb = 100 c 14.3 a i dm (1) (2) drain current (pulsed) 92 a i d (3) drain current (continuous) at tc = 25 c 92 a i d (3) drain current (continuous) at tc = 100 c 57.5 a i dm (2) (3) drain current (pulsed) 368 a p tot (1) total dissipation at t c = 25 c 50 w p tot (3) total dissipation at t pcb = 25 c 2.9 w t stg storage temperature - 55 to 150 c t j operating junction temperature notes: (1) this value is rated according to r thj - c . (2) pulse width limited by safe operating area. (3) this value is rated according to r thj - pcb . table 3: thermal data symbol parameter value unit r thj - pcb (1) thermal resistance junction - pcb max 42.8 c/w r thj - case thermal resistance junction - case max 2.5 c/w notes: (1) when mounted on fr - 4 board of 1 inch2, 2oz cu, t < 10 sec.
electrical characteristics STL23NS3LLH7 4 / 14 docid025074 rev 3 2 electrical characteristics (t c = 25 c unless otherwise specified) table 4: on /off states symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage i d = 1 ma, v gs = 0 v 30 v i dss zero gate voltage drain current v gs = 0 v v ds = 24 v 500 a i gss gate - body leakage current v gs = 20 v, v ds = 0 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 1 ma 1.2 2.3 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 11.5 a 0.0027 0.0037 ? v gs = 4.5 v, i d = 11.5 a 0.004 0.005 ? table 5: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 15 v, f = 1 mhz, v gs = 0 v - 2100 - pf c oss output capacitance - 850 - pf c rss reverse transfer capacitance - 60 - pf q g total gate charge v dd = 10 v, i d = 23 a, v gs = 4.5 v (see figure 13: "gate charge test circuit" ) - 13.7 - nc q gs gate - source charge - 7.5 - nc q gd gate - drain charge - 3.3 - nc table 6: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 15 v, i d = 11.5 a, r g = 3 ?, v gs = 4.5 v - 10 - ns t r rise time - 33 - ns t d(off) turn - off delay time - 22 - ns t f fall time - 7.5 - ns
STL23NS3LLH7 electrical characteristics docid025074 rev 3 5 / 14 table 7: source drain diode symbol parameter test conditions min. typ. max. unit v sd (1) forward on voltage i sd = 2 a, v gs = 0 - 0.4 0.7 v t rr reverse recovery time i sd = 2 a, di/dt = 100 a/s v gs = 0 v - 31.2 ns q rr reverse recovery charge - 18.7 nc i rrm reverse recovery current - 1.2 a notes: (1) pulsed: pulse duration = 300 s, duty cycle 1.5%.
electrical characteristics STL23NS3LLH7 6 / 14 docid025074 rev 3 2.1 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance gipg20022015 11 15m t v ds = 2 v i d 100 50 0 0 v gs (v) (a) 2 gipg200220151026m t i d 100 10 0.1 1 v ds (v) 10 (a) operation in this area is limited by max r ds(on) 1ms 100s 1 tj=150c t c=25c single pulse 10ms gipg200220151051m t 0.05 0.02 0.01 0.1 0.2 gipg20022015 1 129m t r ds(on) 2.50 2.40 2.30 0 5 i d (a) ( mohm ) 2.60 v gs =10v 10 2.70 2.80 2.90 25 20 15 3.00 gipg20022015 1 123m t v gs 3 2 1 0 0 q g (nc) (v) 4 v dd =15v i d =23 a 2 5 4 6 8 10 12 14 gipg20022015 11 12m t i d 0 0 0.4 v ds (v) 0.8 (a) 1.2 v gs =5, 6, 7v 10 20 1.6 4v 3v 30 40
STL23NS3LLH7 electrical characteristics docid025074 rev 3 7 / 14 figure 8 : capacitance variations figure 9 : normalized on - resistance vs temperature figure 10 : normalized v (br)dss vs temperature figure 11 : source - drain diode forward characteristics c 1000 100 10 0.1 10 v ds (v) (pf) 1 ciss coss crss gipg20022015 1 138m t gipg200220151338m t r ds(on) 1.90 1.30 0.90 0.50 -75 t j (c) (norm) -25 75 25 0.70 1.10 1.50 1.70 v gs =10v 125 i d = 1 1.5 a gipg200220151327m t v (br)dss -75 t j (c) (norm) -25 75 25 125 0.94 0.96 0.98 1.00 i d =1m a 1.02 1.04 1.06 gipg200220151216m t v sd 0 10 i sd (a) (v) 20 0.35 0.45 0.55 0.65 t j =-50c t j =150c t j =25c 0.75 0.85
test circuits STL23NS3LLH7 8 / 14 docid025074 rev 3 3 test circuits figure 12 : switching times test circuit for resistive load figure 13 : gate charge test circuit figure 14 : test circuit for inductive load switching and diode recovery times figure 15 : unclamped inductive load test circuit figure 16 : unclamped inductive waveform figure 17 : switching time waveform
STL23NS3LLH7 package information docid025074 rev 3 9 / 14 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package information STL23NS3LLH7 10 / 14 docid025074 rev 3 4.1 powerflat 3.3 x 3.3 package information figure 18 : powerflat? 3.3 x 3.3 package outline
STL23NS3LLH7 package information docid025074 rev 3 11 / 14 table 8: powerflat? 3.3 x 3.3 mechanical data dim. mm min. typ. max. a 0.70 0.80 0.90 b 0.25 0.30 0.39 c 0.14 0.15 0.20 d 3.10 3.30 3.50 d1 3.05 3.15 3.25 d2 2.15 2.25 2.35 e 0.55 0.65 0.75 e 3.10 3.30 3.50 e1 2.90 3.00 3.10 e2 1.60 1.70 1.80 h 0.25 0.40 0.55 k 0.65 0.75 0.85 l 0.30 0.45 0.60 l1 0.05 0.15 0.25 l2 0.15 8 10 12
package information STL23NS3LLH7 12 / 14 docid025074 rev 3 figure 19 : powerflat? 3.3 x 3.3 recommended footprint (dimension in millimeters)
STL23NS3LLH7 revision history docid025074 rev 3 13 / 14 5 revision history table 9: document revision history date revision changes 31 - jul - 2013 1 first release. 27 - mar - 2015 2 updated title and features in cover page. updated table 2: "absolute maximum ratings" , table 4: "on /off states" and table 7: "source drain diode" . added section 2.1: "electrical characteristics (curves)" . minor text changes. 07 - may - 2015 3 document status promoted from preliminary data to production data. minor text changes.
STL23NS3LLH7 14 / 14 docid025074 rev 3 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics C all rights reserved

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